Semiconductor memory devices largely comprise RAMs (Random Access Memories) and ROMs (Read Only Memories). RAM is referred to as volatile memory, in that when supply voltage is removed, data is destroyed with the passage of time. RAM devices, including DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), generally allow for relatively rapid data storage and retrieval. ROM devices, including PROMs (Programmable ROMs), EPROMs (Erasable PROMs), and EEPROMs (Electrically EPROMs) are non-volatile, in that they retain data once it is entered regardless of whether voltage is removed; however, data storage and retrieval in ROM is relatively slow. Demand for EEPROMs, which can electrically program and erase data, is increasing. Such EEPROM cells, or flash memory cells whose contents can be simultaneously erased, are characterized by a stacked gate structure comprising a floating gate and a control gate.
Flash memory cells are generally grouped into NAND type and NOR type circuits NAND type flash memory, in which a unit string is composed of n cell transistors connected in series and such unit strings are connected in parallel between bit lines and ground lines, is useful in realizing high integration. The NOR type, in which respective cell transistors are connected in parallel between bit lines and ground lines, offers high-speed operation. The structure and operation of a basic NOR flash memory cell, disclosed in U.S. Pat. No. 4,698,787 and incorporated herein by reference, is now described with reference to FIGS. 1, 2, and 3.
FIG. 1 is a partial layout diagram of a cell array in a NOR flash memory device, FIG. 2 is an equivalent circuit diagram of the cell array, and FIG. 3 is a vertical sectional view of a unit cell. Referring to FIG. 3, reference numeral 10 denotes a semiconductor substrate, reference numeral 12 denotes a tunnel oxide film, reference numeral 14 denotes a floating gate, reference numeral 16 denotes an interpoly dielectric layer, reference numeral 18 denotes a control gate, reference numerals 20 and 22 denote source/drain regions of the unit cell, respectively, and reference numeral 24 denotes a bit line contact.
Referring to FIGS. 1, 2, and 3, a unit cell is formed in a stacked gate structure comprising a floating gate 14 and a control gate 18 in an area where a word line W/L perpendicularly intersects a bit line B/L, the word and bit lines themselves comprising a metal layer. A plurality of cells are configured in cell arrays, each array including a plurality of bit lines B/Ls, word lines W/Ls, and source lines CSLs, arranged in predetermined intervals. Two cells are connected to a bit line B/L through a bit line contact 24, and source regions of respective cells, comprising impurity diffusion layers parallel to a word line W/L, are connected by a source line CSL, provided every few bits, and disposed in parallel with the bit lines B/L.
In the unit cell shown in FIG. 3, the tunnel oxide film 12 is interposed between the floating gate 14 and the substrate 10, and the interpoly dielectric layer 16 is interposed between the floating gate 14 and the control gate 18 provided as a word line W/L. Further, the source/drain regions 20 and 22 are formed in self-alignment with the stacked gate. The floating gate 14 extends across an active region and portions of edges of field regions at both sides of the active region, thus being isolated from a floating gate 14 of an adjacent cell. The control gate 18 is connected to that of an adjacent cell, forming a word line W/L.
Adjacent cells are formed in opposite directions, sharing the source/drain regions 20 and 22. The drain region 22 of the unit cell is connected with that of an adjacent cell in the same column, and has the bit line contact 24 formed therein. Bit line contacts 24 are electrically connected by a bit line B/L perpendicular to a word line W/L. That is, two cells are connected to a bit line B/L through one bit line contact 24.
The source region 20 of the unit cell is connected to that of an adjacent cell in the same column through a source active region comprising an impurity diffusion layer parallel to a word line W/L. To reduce the resistance of the source line CSL, a source line contact is formed for every plurality of bit lines, in the source active region parallel to the word line W/L. The source line CSL parallel to the bit line B/L is electrically connected to the source active region via the source line contact.
Programming and erasing of the above NOR flash memory cells are based on injection of channel hot electrons (CHEs) and Fowler-Nordheim tunneling through a source or a bulk substrate, respectively.
For a programming operation, the threshold voltage Vth of the cell is raised from an initial level of about 2 V, to a level of about 7 V by storing electrons on a floating gate. That is, by applying 6-7 V to a selected bit line, 10-12 V to a selected word line used as a control gate, and 0 V to a source and a substrate, part of the CHEs are injected onto the floating gate through a tunnel oxide film due to a gate field, and thus the cell is programmed.
For an erasing operation, the threshold voltage Vth is dropped to the initial level of about 2 V, by discharging electrons from the floating gate. That is, by floating the selected bit line, and by applying 12-15 V to the source and 0 V to the selected word line, the electrons tunnel according to the Fowler-Nordheim effect from the floating gate to a source junction, through the tunnel oxide film of approximately 100 .ANG. in thickness, due to the voltage difference between the floating gate and the source junction, and thus the cell is erased. The erasing operation is implemented by a simultaneous block erase technique, that is, by simultaneously erasing hundreds or thousands of bits including multiple word lines and bit lines as a block.
A reading operation refers to determining the absence or presence of a current path through erased and programmed cells by applying approximately 1 V to the selected bit line and 4-5 V to a word line.
The source line CSL operates to inject a large amount of current across the cell to a ground node during programming and reading. In a flash memory cell relying on CHE injection, a source line is formed for every eight or sixteen cells to rapidly discharge a large amount of current.
A drawback of the thus-constituted NOR flash memory device is overerasure-induced disturbance. Overerasure indicates that the erase threshold voltage of a specific cell drops to or below 0 V (a normal erase threshold voltage is 2 V) because process defects in a unit cell or degradation of the tunnel oxide film varies the tunneling field. Generally, a selected cell should be programmed by injecting current only through the selected cell connected to a selected bit line receiving a 6 V programming voltage and a selected word line receiving 12 V. However, in the presence of an overerased cell on an unselected word line held at 0 V, a bit line voltage is discharged through the unselected cell due to the threshold voltage of 0 V or below, thereby reducing the amount of current across the selected cell. As a result, generation of CHEs required for programming of the cell is suppressed and the selected cell fails to be programmed. Furthermore, during a reading operation, an abnormal current path through the unselected overerased cell may lead to the false reading that the selected programmed cell is overerased.
To circumvent this overerasure problem, a NOR flash memory cell is disclosed in U.S. Pat. No. 4,888,734, incorporated herein by reference, wherein a source select transistor is formed between a source line and a source active region. FIG. 4 is a layout diagram of such a cell and FIG. 5 is an equivalent circuit diagram of the cell shown in FIG. 4.
Referring to FIGS. 4 and 5, a source active region 66 of the cell is separated by a source select transistor formed in an overlap area of a source line CSL and a word line W/L so that even if an unselected cell is overerased, the threshold voltage of the source select transistor is maintained at 0 V or higher and the programming and erase voltages of an unselected word line is 0 V. Thus, the conventional overerasure problem is alleviated to some degree, without increasing the area of the cell.
However, because two symmetrical cells (e.g., cell A and cell B in FIG. 5) connected to the same bit line B/L through different bit line contacts 64 share a single source active region 66, possible overerasing of a symmetrical cell sharing the source active region 66 with the cell of a selected word line produces a current path through the overerased cell, resulting in the aforementioned problems.
The following is a detailed description of erasing, programming, and reading operations of the above cell in connection with FIG. 5.
To erase the cell, the threshold voltage of the cell is lowered to approximately 2 V by applying an erase voltage of 12 V to a bit line and 0 V to a gate, thus removing electrons from a floating gate to a drain region via an electric field between a drain and the floating gate.
To describe a programming operation, cell A is taken as an example. A current flows through cell A by applying 6 V to a bit line B/L A, 12 V to a gate, and 0 V to a source and a bulk substrate, and a portion of the CHEs generated by a horizontal field at the drain region are injected onto the floating gate by a vertical field to the gate. In this manner, the threshold voltage of the cell is increased to 7 V or higher. When cell C is overerased, a voltage of 0 V on an unselected word line W/L C prevents a source select transistor C from being activated. Hence, no current path is formed from cell C to the source line CSL, with CSL being a ground node. On the other hand, when cell B is overerased, a bit line current across cell B flows not through a source select transistor B on a word line W/L B held at 0 V, but instead through a source select transistor A sharing the source active region 66. Because of an unintended current path through the unselected cell during a programming operation, current does not flow sufficiently across the selected cell, thereby failing to program the cell.
Reading of a cell is achieved by applying approximately 1 V to a selected bit line and 4-5 V to a selected word line and determining the programmed and erased states of a cell from turn-on and turn-off currents of the cell. When cell B is overerased during the reading of cell A, a current path is generated across cell B with the voltage 0 V on an unselected word line, and thus the selected cell A is misread as an overerased cell.
Another layout cell structure to address the above overerasure problem is disclosed in U.S. Pat. No. 4,888,734, and illustrated in FIG. 6.
Referring to FIG. 6, an independent source select gate line 68 is formed to isolate two cells from each other, which share an identical source active region and are connected to the same bit line B/L through different bit line contacts 64. Since the source select gate line 68 blocks formation of a current path through a source select transistor for another cell sharing the source active region, the above overerasure problem is mitigated. Yet, the entire cell area is increased by the source select gate line 68, making it difficult to realize high integration.
The NOR flash memory cell disclosed in U.S. Pat. No. 4,888,734 exhibits shortcomings which are now described with reference to FIGS. 7A, 7B, and 7C, which are vertical sectional views of FIG. 4, taken along lines a--a', b--b', and c--c', respectively. The problems are manifested when a stacked gate process is performed by self-aligned etching to form a floating gate 54 and a control gate 58 without misalignment.
Referring to FIGS. 7A, 7B, and 7C, a tunnel oxide film 52 is formed on a semiconductor substrate 50 having a field oxide film 51 formed thereon, and a first polysilicon layer 54 for a floating gate is formed on the tunnel oxide film 52. Floating gates of respective cells are isolated from one another by etching the polysilicon layer 54 on the field oxide film 51 by photolithography. Subsequently, an interpoly dielectric later 56 is formed on the resultant structure and a second polysilicon layer 58 for a control gate is formed on the interpoly dielectric layer 56. After a photoresist pattern 59 is formed on the second polysilicon layer 58 to form a word line, a stacked gate is formed by sequentially etching the second polysilicon layer 58, the interpoly dielectric layer 56, and the first polysilicon layer 54 using the photoresist pattern 59 as an etching mask. The space between floating gates 54 corresponds to a portion of the field oxide film 51. The exposed field oxide film 51 may be etched during etching of the floating gate 54, but this is not likely, as etch selectivity with polysilicon and oxide is generally excellent in a dry etching process.
However, for formation of a source select transistor having a MOS single-layer gate structure in a cell array of a stacked gate structure, the first polysilicon layer 54 for a floating gate is not formed on a source active region because only the control gate 58 acts as the gate of the source select transistor. Hence, when the first polysilicon layer 54 for a floating gate is etched after self-aligned etching of the second polysilicon layer 58 for a control gate and the interpoly dielectric layer 56, source/drain active regions 60 and 62 of the exposed source select transistor are likewise etched at the same etch rate and are therefore damaged (see FIG. 7C).
Further, when a source select gate line is to be formed in the cell, use of a high-voltage source erase method (i.e., applying 0 V to a gate and an erase voltage to a source) impedes an erase voltage applied to a source line from transferring to a source active region because the voltage on a selected word line is 0 V, lower than the threshold voltage of the source select transistor. Therefore, to solve this problem, a high-voltage drain erase method (i.e., applying 0 V to the gate and an erase voltage to a drain) is used instead, and the drain is formed to be a double diffused (DD) junction structure so that the bit line junction is not destroyed at 10 V or higher and leakage current is suppressed. As a result, generation of hot electrons is suppressed and programming efficiency is reduced, as compared to a general cell having a drain of an abrupt junction for CHE injection programming. In addition, if a drain acts as both programming and erase junctions, a tunnel oxide film may be rapidly degraded at a drain region due to injection and removal of electrons into and from the drain region.